As the number of I/O interconnections to integrated circuit chip increases, forming the required number of I/O pads around the chip periphery becomes impractical. One solution which provides increased I/O density is the "flip chip" package. The flip chip package has an area array configuration which increases the number of interconnections available compared to standard IC packages. Instead of electrically interconnecting the chip using wire bonding techniques, solder bumps are formed on the input/output pads of the chip. The chip is flipped so that its solder bumps are aligned to a connecting pattern formed on a ceramic substrate. The temperature is then increased to cause the solder bumps to reflow for direct bonding of the I/O pads of the chip to contact sites on the substrate.
To improve device reliability the chip is insulated from the environment and from mechanical stresses initiated by the heat sink by surrounding the chip with a sealed lid. Typically, the lid is a unitary structure formed from a conductive material. The lid serves to convey directly mechanical stress from the heat sink to the ceramic substrate instead of through the chip. The mechanical stress from the heat sink results from momentum changes imparted to the heat sink (large mass) during velocity changes caused by mechanical shock and/or vibrations.
Referring to FIGS. 1A-C, FIG. 1A shows a package 100 which provides a semi-hermetic seal by mechanically contacting the lid 102 to the substrate 104 with an adhesive seal 106. In the package 100 of FIG. 1A, inset FIG. 1C shows, the rim 108 of the package lid 102 directly contacts the substrate 104 so that lid placement is held by the sealant 106 which forms a fillet on the sides of the lid rim 108. Since the height 118 of the lid rim 108 is greater than the summation of the heights of the chip 110 and the electrical interconnections 112 between the chip 110 and the substrate 104, sufficient die attach material 114 must be placed on the chip backside (or the lid ceiling) to fill the space between the chip 110 and the lid ceiling 116. One problem with this approach is that the clearance between the chip 110 and the lid ceiling 116 varies dependent on the sum of the variations in the lid depth, the chip thickness, the height of the solder bumps and other variables. This variation in clearance, in turn, translates into a variation in the thickness of the die attach material. This variance in die attach material thickness results in varying thermal resistance making thermal performance of the package uncertain.
In order to overcome the inconsistency in thermal performance of the previously described package, a package structure and method of formation disclosed in a case filed Oct. 10, 1994, having Ser. No. 319,764 was described and is shown in FIGS. 2A-C. The package lid 206 of package structure 200 is typically formed of a Kovar ring structure 214 and a copper tungsten (CuW) coverplate 216 which are brazed together before attachment to the substrate 208. In contrast to the previously described system shown in FIGS. 1A-C, a predetermined thickness of die attach material 202 is applied between the chip 204 and lid 206 so that thermal performance is certain. Further, the height 218 of the rim of the lid is made less than the summation of the heights of the chip 204, the electrical interconnections between the chip 204 and the substrate 208, and the die attach layer 202. The clearance between the rim 210 of the lid and the substrate 208 is filled with a lid attach material 212 having a height 220. Thus, instead of the die attach material 202 taking into account variances in chip thickness, solder bump height, etc., in the package shown in FIGS. 2A-C variances are taken into account by the lid attach material 212 between the rim of the lid and the substrate 208.
Although the package shown in FIGS. 2A-C reduces problems of thermal inconsistency, the package shown in FIGS. 2A-C increases mechanical stress to the chip compared to the package in FIG. 1. Excess mechanical stress is problematic in that it may fracture the chip or alternatively may create microcracks which propagate through the chip and may result in device failure. In FIGS. 1A-C, stress applied to the package lid will be disproportionately transferred to the ceramic substrate compared to the stresses applied to the chip. Because in the embodiment of FIGS. 2A-C attachment between the lid rim and substrate does not provide as firm a mechanical contact as the direct contact shown in FIGS. 1A-C, increased mechanical stress will be delivered to the chip.
A package that provides a repeatable low thermal resistance value, consistency in fabrication and low mechanical stress to the chip at a low cost is needed.